The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 임베디드 프로세서를 위한 누출 효율적인 데이터 TLB(Translation Look-aside Buffer) 설계를 제시합니다. 프로그램의 데이터 지역성으로 인해 데이터 TLB 참조는 짧은 실행 간격 동안 적은 수의 페이지에만 도달하는 경향이 있습니다. 전체 실행 시간을 더 작은 시간 조각으로 나눈 후 각 시간 조각 내에서 가상-물리적 주소 변환에 실제로 사용되는 TLB 항목을 감지하기 위한 누출 감소 메커니즘이 제안됩니다. 따라서 이중 전압 공급 기술을 통합하면 주소 변환에 사용되지 않는 TLB 항목을 낮은 누설 모드(낮은 전압 공급)로 전환하여 전력을 절약할 수 있습니다. 37개의 MiBench 프로그램을 사용한 평가 결과, 제안된 설계는 데이터 TLB의 누출 전력을 평균 0.01% 감소시키고 성능 저하를 XNUMX% 미만으로 줄일 수 있는 것으로 나타났습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, "A Leakage Efficient Data TLB Design for Embedded Processors" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 1, pp. 51-59, January 2011, doi: 10.1587/transinf.E94.D.51.
Abstract: This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.51/_p
부
@ARTICLE{e94-d_1_51,
author={Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Leakage Efficient Data TLB Design for Embedded Processors},
year={2011},
volume={E94-D},
number={1},
pages={51-59},
abstract={This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.},
keywords={},
doi={10.1587/transinf.E94.D.51},
ISSN={1745-1361},
month={January},}
부
TY - JOUR
TI - A Leakage Efficient Data TLB Design for Embedded Processors
T2 - IEICE TRANSACTIONS on Information
SP - 51
EP - 59
AU - Zhao LEI
AU - Hui XU
AU - Daisuke IKEBUCHI
AU - Tetsuya SUNATA
AU - Mitaro NAMIKI
AU - Hideharu AMANO
PY - 2011
DO - 10.1587/transinf.E94.D.51
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2011
AB - This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
ER -