The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
강력한 로컬 이미지 기능은 많은 최첨단 컴퓨터 비전 알고리즘의 중요한 구성 요소가 되었습니다. 제한된 하드웨어 리소스로 인해 임베디드 시스템의 로컬 기능을 계산하는 것은 쉬운 작업이 아닙니다. 본 논문에서는 다중 DSP 기반 임베디드 시스템을 지향하면서 빠르고 강력한 기능을 위한 효율적인 병렬 컴퓨팅 프레임워크를 제안합니다. 우리는 DSP 칩의 기능을 더 잘 활용하기 위해 SURF의 모듈을 최적화합니다. 또한 제한된 메모리 리소스에 적응하고 데이터 액세스 대역폭을 늘리기 위해 컴팩트한 데이터 레이아웃을 설계합니다. 병렬 작업 칩을 동기화하고 전체 비용을 절감하기 위해 데이터 기반 장벽과 작업 부하 균형 체계가 제시됩니다. 실험은 우리의 구현이 관련 작업에 비해 경쟁력 있는 시간 효율성을 달성한다는 것을 보여줍니다.
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Chao LIAO, Guijin WANG, Quan MIAO, Zhiguo WANG, Chenbo SHI, Xinggang LIN, "DSP-Based Parallel Implementation of Speeded-Up Robust Features" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 4, pp. 930-933, April 2011, doi: 10.1587/transinf.E94.D.930.
Abstract: Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.930/_p
부
@ARTICLE{e94-d_4_930,
author={Chao LIAO, Guijin WANG, Quan MIAO, Zhiguo WANG, Chenbo SHI, Xinggang LIN, },
journal={IEICE TRANSACTIONS on Information},
title={DSP-Based Parallel Implementation of Speeded-Up Robust Features},
year={2011},
volume={E94-D},
number={4},
pages={930-933},
abstract={Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.},
keywords={},
doi={10.1587/transinf.E94.D.930},
ISSN={1745-1361},
month={April},}
부
TY - JOUR
TI - DSP-Based Parallel Implementation of Speeded-Up Robust Features
T2 - IEICE TRANSACTIONS on Information
SP - 930
EP - 933
AU - Chao LIAO
AU - Guijin WANG
AU - Quan MIAO
AU - Zhiguo WANG
AU - Chenbo SHI
AU - Xinggang LIN
PY - 2011
DO - 10.1587/transinf.E94.D.930
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2011
AB - Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.
ER -